Title :
Access time and energy tradeoffs for caches in high frequency microprocessors
Author :
John, Eugene B. ; Petko, Stefan ; John, Lizy Kurian ; Law, Jason
Author_Institution :
Electr. & Comput. Eng. Dept., Texas Univ., San Antonio, TX, USA
Abstract :
This paper investigates the cache sizes and configurations that can be supported by a high frequency processor of the next generation. Based on the SIA roadmap prediction that a 0.1 μm processor of the next generation will run at 3.5 GHz, we model caches of that technology using the CACTI tool. Access times as well as energy consumption are modeled for caches in the 8 K-4 M range, for various associativities. Impact of having multiple ports as well as that of varying block sizes is also studied.
Keywords :
cache storage; integrated circuit design; integrated circuit modelling; logic design; microprocessor chips; 0.1 micron; 3.5 GHz; 8 Kbyte to 4 Mbyte; cache access time; cache associativity; cache configuration; cache energy tradeoffs; cache size; energy consumption; high frequency microprocessors; multiple ports; varying block sizes; Clocks; Electronics industry; Energy consumption; Frequency; High performance computing; Integrated circuit technology; Microprocessor chips; Power engineering and energy; Predictive models; Transistors;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187063
