A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications

Author

Juarez-Hernández, Esdras ; Díaz-Sánchez, Alejandro

Author_Institution

Instituto Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico

Volume

3

fYear

2002

fDate

4-7 Aug. 2002

Abstract

The design and simulation of a 1.35 GHz CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wideband PLL topology with a high frequency reference, giving as result low phase noise, fast switching time, a low divider ratio and a reduction in the chip area. Besides, the use of a novel charge-pump circuit with positive feedback and current reuse allows a further reduction in both, chip area and power consumption, making the structure desirable for high-frequency low-voltage phase-locked loops.

Keywords

CMOS analogue integrated circuits; cellular radio; frequency synthesizers; low-power electronics; phase locked loops; phase noise; 1.35 GHz; CMOS; charge-pump circuit; chip area; current reuse; divider ratio; double band receiver; frequency reference; low-voltage phase-locked loops; mobile communications; phase noise; positive feedback; power consumption; switching time; wideband PLL topology; wideband frequency synthesizer; Charge pumps; Circuit topology; Communication switching; Feedback circuits; Frequency conversion; Frequency synthesizers; Mobile communication; Phase locked loops; Phase noise; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1187086

Filename

1187086