Characterizing metastability and jitter in CMOS latch/flip-flop used as a digital mixer

A novel low power silicon-on-insulator (SOI) CMOS digital mixer circuit that is small, fully integrable and easily implemented is presented. This circuit is for use in a microbalance counter circuit (MBC) that operates at temperatures up to 180 degrees Celsius for petroleum industry well logging applications and has a measurement acquisition time of 2.4 seconds and a frequency resolution of 59 nHz when measuring 7 MHz signals. The digital mixer circuit eliminates the need for an analog mixer and bulky, temperature sensitive low pass filter components. This paper focuses on modeling and analysis of the metastable behavior and measurement inaccuracy caused by input phase jitter of the digital mixer. There is a risk of miscount due to jitter in the input signals. This paper explains how to model this risk and generate design parameters given the user´s criteria for maximum risk of count errors.