HDL synthesis and simulation of eight bit DSP based micro-controller for image processing applications

This paper deals with VLSI design and simulation of fast eight bit DSP based RISC micro controller for real time image processing applications. By exploiting inherent concurrency of two dimension recursive filters, Folded systolic architecture is designed and combined with HAVARD architecture. Due to pipelined features each instruction takes one clock period for execution. Apart from ALU, program memory (PRAM), data memory (CROM), four register banks, two stacks are incorporated in design. Control signals for folded architecture is generated in the HAVARD architecture of RISC processor. The folded architecture has seven column processors which are capable of handling forty-nine pixels in forty-nine clock periods. Each column processor has fixed point adder multiplier, latch and enable pin. The core has been designed using Verilog as HDL with SPARTAN SQSVQ100 as target FPGA device. Waveform of functional simulation of core confirms the micro-controller´s capability of having throughput rate of ONE PIXEL PER CLOCK PERIOD.