An analog turbo decoder for an (8,4) product code

This paper illustrates how analog circuitry can be used to decode turbo and turbo-like codes. For ease of exposition, the focus is on a simple two dimensional product code comprised of a 2 by 2 array of (3,2) single parity check codes. It is shown that the heart of the decoder is a soft exclusive-or operation which is easily implemented in analog as a modified Gilbert multiplier. Finally, a complete decoder design is presented which is capable of achieving throughput on the order of hundreds of Mbps.