Title :
Signal Integrity Analysis with Power Delivery Network
Author :
Rangaswamy, Granthana K. ; Prathaban, Satish
Author_Institution :
Intel Corp., Bangalore
Abstract :
Increased frequencies and reduced rise times have made signal integrity simulations an integral part of high speed board designs. Signal integrity simulations are usually performed considering an ideal power source and power integrity simulations are performed assuming ideal transmission lines. But due to ever decreasing rise times errors creep into signal quality and timing analysis by ignoring the effects of the PDN. This paper outlines the necessity and the impact of including power delivery network effects for signal quality and timing analysis. This paper highlights the combined effort of signal integrity and power delivery simulations which are performed to obtain the optimal topology, terminations and decoupling solution for motherboard implementation of 533MT/s DDR2 devices that are soldered directly on the motherboard
Keywords :
network topology; printed circuit design; 533MT/s DDR2 devices; high speed board designs; motherboard; optimal topology; power delivery network; signal integrity analysis; signal quality; timing analysis; transmission lines; Analytical models; Frequency; Impedance; Performance analysis; Power transmission lines; Rails; Signal analysis; Timing; Transmission line theory; Voltage;
Conference_Titel :
Signal Propagation on Interconnects, 2006. IEEE Workshop on
Conference_Location :
Berlin, Germany
Print_ISBN :
1-4244-0455-x
Electronic_ISBN :
1-4244-0455-x
DOI :
10.1109/SPI.2006.289221