Planar Transmission Line Structures as Possible On-Chip Interconnects in Deep Sub-Micron (DSM) Processes

The paper proposes the possible use of planar transmission line structures (i.e. coplanar, microstrip, stripline etc.) as on-chip interconnects in deep sub-micron (i.e. 65 nm) as it is observed that the traditional style of forming bus structures for reliable high speed data transfer fails to provide up-to-the-mark performance. It is shown that planar transmission line structures can be an attractive choice for on-chip interconnects with reduced crosstalk noise generation and comparable data rate. Here the simulation techniques have been used to justify the possible use of planar transmission line structures as possible on-chip interconnects