A fourth-order cascaded sigma-delta modulator with DAC error cancellation technique

Author

Su, C.H. ; Chao, K.S.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Tech. Univ., Lubbock, TX, USA

Volume

1

fYear

2002

fDate

4-7 Aug. 2002

Abstract

An architecture that improves the performance degradation caused by the DAC nonlinearity in a cascaded multibit sigma-delta modulator is presented. The proposed architecture, with an extra feedback path in each internal stage, can totally cancel out the errors caused by the DAC nonlinearity at the final stage and, in general, increases the shaping function of DAC errors by one order for the other internal stages as compared to the MASH structure. Behavioral simulation shows that the proposed fourth-order modulator has excellent immunity of DAC nonlinearity over the MASH structure when OSR is greater than 16. With maximum DAC integral nonlinearity (INL) of ±0.05 LSB and an OSR of 32, an improvement of 15 dB over the MASH structure has been observed.

Keywords

circuit feedback; digital-analogue conversion; sigma-delta modulation; DAC error cancellation technique; DAC nonlinearity; behavioral simulation; cascaded multibit sigma-delta modulator; feedback path; fourth-order cascaded sigma-delta modulator; integral nonlinearity; performance degradation; shaping function; Calibration; Chaos; Computer architecture; Computer errors; Degradation; Delta-sigma modulation; Feedback; Multi-stage noise shaping; Quantization; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1187174

Filename

1187174