A 1.2 μm CMOS deadlock-free router for hypercycle networks

The authors consider deadlock-free routing in hypercycles, which are class of multidimensional graphs used for modeling interconnection networks. Hypercycles offer simple routing, and incremental expansion, variable diameter, enhanced fault-tolerance, and hence can be tailored specifically to the topology of a particular application. The authors consider the hardware implementation of a 1.2μm CMOS chip that implements deadlock preventing routing. The chip consists of about 20,000 transistors and has an expected throughput of 20 million decisions per second