A FPGA based modular coincidence arbitrator design for Compton camera with multiple detection blocks

A field programmable gate array (FPGA) based modular coincidence arbitrator has been designed for the new generation of Compton camera which involves multiple scattering and absorbing detection blocks. Compared with the conventional coincidence trigger generator realized by TAC-SCA modules or separated logic gates, the proposed FPGA design increases the flexibility for coincidence window length adjustment and enables online updates of the look-up-table listing the different combinations of detection blocks that need to be triggered under different inputs. Furthermore, the FPGA design reduces the redevelopment time for modifying detection blocks by using independent function modules. In this design, the coincidence arbitrator is composed of one central control module, several detector coincidence (SD) modules, and one communication module. The central controller is employed to initialize the coincidence window, synchronize the difference detector modules, arbitrate the system coincidence, and trigger the corresponding detection blocks. The SD module, associated with one corresponding detection block, is employed to initialize pulse-delay-timer, delays the pulse generated by the external detector and judges whether that delayed pulse in within the coincidence window. The communication block transmits the states and controllable parameters between the arbitrator and the host PC via the USB port. All the functions of a multiple modular coincidence arbitrator are implemented by the Xilinx Spartan-3 FPGA at the working frequency of 100 MHz