DocumentCode
3298893
Title
Low voltage cascode amplifier
Author
Ardalan, Shahab ; Raahemifar, Kaamran ; Yuan, Fei
Author_Institution
Dept. of Electr. & Comput. Eng., Ryerson University, Toronto, Ont., Canada
Volume
1
fYear
2002
fDate
4-7 Aug. 2002
Abstract
A 0.8 V folded cascode operational amplifier was designed in 0.18 μm standard CMOS technology. Emphasis was placed on observing the low voltage design and using a current driven bulk (CDB) technique to achieve this goal. The CDB technique was introduced as a method for low voltage design by reducing the threshold voltage. This design achieves 141 dB DC gain, 56 MHz 3 dB bandwidth and 65 GHz gain bandwidth, which is the working condition of pipeline ADCs.
Keywords
CMOS analogue integrated circuits; circuit simulation; integrated circuit design; integrated circuit modelling; low-power electronics; operational amplifiers; 0.18 micron; 0.8 V; 141 dB; 56 MHz; CDB technique; CMOS amplifier; current driven bulk technique; folded cascode operational amplifier; low voltage cascode amplifier; pipeline ADC; threshold voltage reduction; CMOS technology; Employee welfare; Equations; Low voltage; MOS devices; MOSFETs; Operational amplifiers; Pipelines; System-on-a-chip; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187208
Filename
1187208
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