Title :
Adjustable CMOS voltage limiters for low-voltage applications
Author :
Silva-Martinez, Jose
Author_Institution :
Nat. Inst. of Astrophys. Opt. & Electron., Puebla, Mexico
Abstract :
This paper deals with the design of CMOS voltage limiters. The proposed topologies are based on the sample and hold principle; wherein the circuits are driven by the comparison of the input signal and a control voltage. The voltage comparison is carried out by using complementary differential pairs for single ended structures or two parallel connected transistors if balanced inputs are available. The resulting topologies are efficient and simple
Keywords :
CMOS analogue integrated circuits; limiters; sample and hold circuits; adjustable CMOS voltage limiters; balanced inputs; complementary differential pairs; low-voltage applications; parallel connected transistors; sample/hold principle; single ended structures; voltage comparison; Capacitors; Circuit topology; Clocks; Equations; Filters; Knee; Leakage current; Switches; Virtual colonoscopy; Voltage control;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.539985
