Title :
Analyzing the simultaneous switching noise due to internal gate switching
Author :
Yang, Li ; Yuan, I.S. ; Hagedorn, M.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL, USA
Abstract :
In this paper, the ground bounce noise due to internal gate switching is studied. It has been found that both power-rail and ground-rail pin impedances are important in evaluating internal ground bounces. Based on the lumped-model analysis taking into account the parasitic effects of MOS transistors, a novel analytical model is developed which accurately accounts for both power rail and ground rail pin impedances. The proposed model is compared with the previous work and validated by SPICE simulation results.
Keywords :
SPICE; integrated circuit modelling; integrated circuit noise; MOS transistor; SPICE simulation; analytical model; ground bounce noise; ground-rail pin impedance; internal gate switching; lumped model; parasitic effect; power-rail pin impedance; simultaneous switching noise; Analytical models; Computer science; Equations; Equivalent circuits; Impedance; MOSFETs; Rails; Surges; Switching circuits; Voltage;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187233
