Motion compensation sample processing for HDTV H.264/AVC decoder

Author

Azevedo, Arnaldo ; Zatt, Bruno ; Agostini, Luciano ; Bampi, Sergio

Author_Institution

Instituto de Informatica, UFRGS, Porto Alegre, Brazil

fYear

2005

fDate

21-22 Nov. 2005

Firstpage

110

Lastpage

113

Abstract

This work present a sample processing architecture to the H.264/AVC, the new video coding standard of the ITU-T and ISO/IEC, main profile motion compensation video decoder. The architecture processes luma and chroma samples in parallel, with one luma and two chroma datapaths. The sample processing is formed by the quarter sample interpolation, weighted prediction, median to bidirectional processing and clipping. The design implemented both in FPGA and VLSI are able to decode HDTV (1080x1920), 30 frames per second, at real-time at 100 and 83.9 MHz clock cycle, respectively.

Keywords

IEC standards; ISO standards; VLSI; field programmable gate arrays; high definition television; logic design; motion compensation; video coding; 100 MHz; 83.9 MHz; HDTV H.264/AVC decoder; IEC standards; ISO standards; ITU-T standards; VLSI; chroma samples; field programmable gate arrays; high definition television; luma samples; motion compensation sample processing; quarter sample interpolation; video decoders; Automatic voltage control; Decoding; Field programmable gate arrays; HDTV; IEC standards; ISO standards; Interpolation; Motion compensation; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP Conference, 2005. 23rd

Print_ISBN

1-4244-0064-3

Type

conf

DOI

10.1109/NORCHP.2005.1597001

Filename

1597001