• DocumentCode
    3299800
  • Title

    Analysis on semantic transactional memory footprint for hardware transactional memory

  • Author

    Chung, Jaewoong ; Chakrabarti, Dhruva R. ; Minh, Chi Cao

  • Author_Institution
    Intel Labs., Santa Clara, CA, USA
  • fYear
    2010
  • fDate
    2-4 Dec. 2010
  • Firstpage
    1
  • Lastpage
    11
  • Abstract
    We analyze various characteristics of semantic transactional memory footprint (STMF) that consists of only the memory accesses the underlying hardware transactional memory (HTM) system has to manage for the correct execution of transactional programs. Our analysis shows that STMF can be significantly smaller than declarative transactional memory footprint (DTMF) that contains all memory accesses within transaction boundaries (i.e., only 8.3% of DTMF in the applications examined). This result encourages processor designers and software toolchain developers to explore new design points for low-cost HTM systems and intelligent software toolchains to find and leverage STMF efficiently. We identify seven code patterns that belong to DTMF, but not to STMF, and show that they take up 91.7% of all memory accesses in transactional boundaries, on average, for the transactional programs examined. A new instruction prefix is proposed to express STMF efficiently, and the existing compiler techniques are examined to check their applicability to deduce STMF from DTMF. Our trace analysis shows that using STMF significantly reduces the ratio of transactions overflowing a 32KB L1 cache, from 12.80% to 2.00%, and substantially lowers the false positive probability of Bloom filters used for transaction signature management, from 23.60% to less than 0.001%. The simulation result shows that the STAMP applications with the STMF expression run 40% faster on average than those with the DTMF expression.
  • Keywords
    cache storage; probability; transaction processing; 32KB L1 cache; Bloom filters; false positive probability; hardware transactional memory; instruction prefix; intelligent software toolchain; memory access; semantic transactional memory footprint; trace analysis; transaction signature management; Arrays; Bioinformatics; Genomics; Hardware; Instruction sets; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Workload Characterization (IISWC), 2010 IEEE International Symposium on
  • Conference_Location
    Atlanta, GA
  • Print_ISBN
    978-1-4244-9297-8
  • Electronic_ISBN
    978-1-4244-9296-1
  • Type

    conf

  • DOI
    10.1109/IISWC.2010.5649529
  • Filename
    5649529