Title :
A low power and reduced area carry select adder
Author :
Rawat, Kuldeep ; Darwish, Tarek ; Bayoumi, Magdy
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Abstract :
A carry select adder (CSA) can be implemented by using a single adder block and an add-one circuit instead of using dual adder blocks. The add-one circuit is based on "first" zero detection logic and a few multiplexers. In the modified CSA, one of the n-bit adder blocks is replaced by an add-one circuit consisting of fewer transistors. This scheme considerably reduces the power and area, with negligible speed penalty. For 8-bit length, n=8, this modified CSA requires 38% fewer transistors and consumes only 73% of the power, compared to the conventional design, using a 0.5 μm CMOS technology.
Keywords :
CMOS logic circuits; adders; carry logic; circuit simulation; integrated circuit design; logic design; logic simulation; low-power electronics; 0.5 micron; 8 bit; CMOS; CSA single adder block; add-one circuit; adder bit length; first zero detection logic; low power adder; multiplexers; power reduction; reduced area carry select adder; Added delay; Adders; Area measurement; CMOS technology; Energy consumption; Integrated circuit measurements; Logic circuits; Multiplexing; Power dissipation; Power measurement;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187259
