Semi floating-gate S/H circuits

Author

Jensen, René ; Berg, Yngvar ; Lomsdalen, Johannes G.

Author_Institution

Dept. of Informatics, Oslo Univ., Norway

fYear

2005

fDate

21-22 Nov. 2005

Firstpage

176

Lastpage

179

Abstract

This paper presents a new proposal for implementing voltage mode sample and hold (S/H) for multiple valued (MV) circuits. The circuits have been implemented using recharged semi floating-gate (SFG) technique for conventional CMOS processes and follows a new SFG S/H latching scheme. The concept is similar to the SFG latch technique. Two circuits for on-chip interconnection of SFG and non-SFG circuits are proposed. One read-in circuit introducing the required interleaved SFG recharge voltage, and one readout circuit capable of restoring the non-interleaved multiple valued voltage. A chip with the proposed circuits has been fabricated in AMS 0.35 μm. Included is measured chip results verifying the operation.

Keywords

CMOS analogue integrated circuits; sample and hold circuits; switched capacitor networks; 0.35 micron; CMOS processes; SFG S/H latching scheme; multiple valued circuits; on-chip interconnection; read-in circuit; readout circuit; sample and hold circuits; semi floating-gate latch technique; Capacitors; Informatics; Integrated circuit interconnections; Inverters; Latches; Nonvolatile memory; Proposals; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP Conference, 2005. 23rd

Print_ISBN

1-4244-0064-3

Type

conf

DOI

10.1109/NORCHP.2005.1597018

Filename

1597018