DocumentCode
3299985
Title
A leakage tolerant energy efficient wide domino circuit technique
Author
Elgebaly, Mohamed ; Sachdev, Manoj
Author_Institution
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Volume
1
fYear
2002
fDate
4-7 Aug. 2002
Abstract
Deep submicron noise, especially leakage current, greatly impacts the performance of wide dynamic gates. Quite often, energy is traded off for increased leakage tolerance. In this paper, a leakage tolerant energy efficient wide domino gate is presented. The proposed technique achieves faster evaluation by splitting the wide gate into two sections and consequently slashing the capacitance of the dynamic node by half. Using the new technique, the same level of leakage tolerance can be achieved with around 12% and 28% reduction in energy for 16-input and 32-input OR gates, respectively, compared to the conventional technique.
Keywords
CMOS logic circuits; VLSI; integrated circuit noise; leakage currents; logic gates; low-power electronics; OR gates; capacitance; deep submicron noise; energy efficient wide domino circuit technique; energy reduction; leakage current; leakage tolerance; wide dynamic gates; Circuit noise; Clocks; Crosstalk; Degradation; Energy efficiency; Leakage current; Logic devices; Noise reduction; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187264
Filename
1187264
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