Failure analysis methodology for gate oxide breakdown induced by PID

In VLSI manufacturing, high density plasma were employed for deposition and etching steps. Damage due to plasma become inevitable and can potentially break the gate dielectric bonds with increasing gate dielectric leakage current resulting in transistor threshold voltage shifts and device failure. In this paper, a systematic and efficient failure analysis methodology to successfully isolate and characterize defect in the channel region due to plasma charge induced damage was presented. The failure mode and mechanism was also presented.