Sequential circuits BIST synthesis from signal specifications

Efficient built-in self-test (BIST) solutions for certain cryptographic applications have been known for a long time. However, area-efficient methods for the general case of sequential circuits are missing. Current paper proposes a novel approach to BIST synthesis for synchronous sequential circuits. The approach is based on designer´s specification of the control signal modes. Relying on that formal specification BIST structures are created and fault simulated in order to assess the fault coverage. An optimal solution is selected and corresponding BIST hardware is synthesized from the signal specification. Additional benefit of the approach is to provide for high-quality test patterns for cores lacking scan infrastructure as commercial ATPG tools able to efficiently handle sequential cores exceeding couple of thousands logic gates are currently missing. The experiments show that high quality tests and BIST structures can be obtained by implementing the proposed method for non-scan cores.