Title :
Topography and Deformation Measurement and FE Modeling applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs)
Author :
Hert, M. ; Carniello, S. ; Cassidy, C.
Author_Institution :
Insidix, Grenoble, France
Abstract :
Topography and Deformation Measurement and FE Modeling were applied for characterization of the warpage vs. temperature behavior of several different die stacks, with or without Through Silicon Vias, for sample temperatures from 25°C...250°C. The warpage behavior is of fundamental importance for the lifetime and reliability expectation of the stack.
Keywords :
deformation; finite element analysis; reliability; wafer level packaging; FE modeling; TSV; deformation measurement; die stacks; stack reliability; substrate-mounted large area wafer-level packages; temperature 25 degC to 250 degC; through silicon vias; topography; Area measurement; Deformable models; Iron; Packaging; Plasma temperature; Semiconductor device modeling; Surfaces; Thermal stresses; Wafer bonding; Wafer scale integration;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium on the
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-5596-6
DOI :
10.1109/IPFA.2010.5532239
