Automatic synthesis of asynchronous circuits from synchronous RTL descriptions

As the dimensions of ASICs shrink down to the nanometer regime, the variability of the process parameters will increase. This variability threatens to make it extremely difficult to distribute a synchronous clock all over the chip. Another option would be to replace critical synchronous parts with asynchronous counterparts with the same functionality. The main problems are, first, there is no established tool-flow that makes it easy for a designer to design an asynchronous circuits, and, second, there are no established design automation tools, except a few experimental ones. In addition, most designers today are trained to design synchronous circuits and have to be retrained. In this paper, we present a method that solves all three of these problems, i.e., it allows a designer to start in the synchronous domain, and then automatically transform the synchronous representation of the circuit into an asynchronous one.