DocumentCode :
3300056
Title :
A compact software-controlled clock multiplier for SoC application
Author :
Pao-Lung Chen ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
1
fYear :
2002
fDate :
4-7 Aug. 2002
Abstract :
A compact software-controlled clock multiplier for SoC application is presented in this paper. The control mechanism of clock multiplier includes frequency acquisition, phase acquisition and phase/frequency maintenance modes; these operations sequence are programmable. Our proposed clock multiplier is integrated with an 8-bit microcontroller in order to verify the proposed software-controlled mechanism. The control mechanism is shared with the computing power of microcontroller. A proto-type chip has been implemented with 0.35 μm 1P4M CMOS process that can operate from 25 MHz to 80 MHz. The multiplication factor can range from 2 to 128 and software instructions are less than 90 instructions. Thus it not only reduces the cost and design complexity of clock multiplier, but also offers particular advantages, especially when computing power is already available.
Keywords :
CMOS logic circuits; multiplying circuits; system-on-chip; 0.35 micron; 25 to 80 MHz; CMOS; SoC application; design complexity; frequency acquisition; multiplication factor; phase acquisition; phase/frequency maintenance modes; software-controlled clock multiplier; Application software; CMOS process; Clocks; Digital filters; Digital signal processors; Frequency; Microcontrollers; Phase locked loops; Signal processing algorithms; Software performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
Type :
conf
DOI :
10.1109/MWSCAS.2002.1187267
Filename :
1187267
Link To Document :
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