DocumentCode :
3300113
Title :
Bus-invert coding for LUT-based FPGAs
Author :
Knittel, G.
Author_Institution :
Tuebingen Univ., Germany
fYear :
2005
fDate :
21-22 Nov. 2005
Firstpage :
218
Lastpage :
221
Abstract :
We describe an approximative implementation of bus-invert coding for LUT-based FPGAs driving an external bus through dual-data-rate outputs. The majority voter circuit, typically implemented as a tree of full-adders, is the performance-limiting unit, and is replaced by an inexact interval logic. For a 16-bit bus, logic depth is limited to five stages of 4-input LUTs. Compared to an adder-tree implementation, propagation delay of the inexact majority voter is approximately one half. The disadvantage is that signal transition statistic is suboptimal, and the maximum number of simultaneous signal changes is increased to 10 in rare cases.
Keywords :
adders; encoding; field programmable gate arrays; table lookup; 16 bit; LUT-based FPGA; bus-invert coding; dual-data-rate outputs; field programmable gate arrays; full-adder-tree implementation; inexact interval logic; lookup tables; majority voter circuit; Bit rate; Capacitance; Circuits; Crosstalk; Field programmable gate arrays; Hardware; Power dissipation; Propagation delay; Table lookup; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
NORCHIP Conference, 2005. 23rd
Print_ISBN :
1-4244-0064-3
Type :
conf
DOI :
10.1109/NORCHP.2005.1597028
Filename :
1597028
Link To Document :
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