Multiply-add fused RISC architectures for DSP applications

The development of a fixed-point bit-parallel multiply-add fused (MAF) architecture together with a corresponding VLSI implementation is presented. The proposed MAF implementation employs 1.2μ CMOS technology. This MAF implementation finds a variety of practical applications in high-speed real-time digital signal processing. The MAF implementation employs a parallel modified Booth multiplier incorporating an array of carry-save adders for the addition of the intermediate partial products, and a hardware efficient carry-skip adder for carry propagation. The performance characteristics of the MAF implementation have been successfully verified by an HSPICE simulation at speeds of up to 100 MHz