Title :
Scaling of serially-connected MOS transistors with constant area constraint
Author :
Elkammar, Ahmed N ; Vermuru, S.R.
Author_Institution :
Dept. of Electr. Eng., City Coll. of New York, NY, USA
Abstract :
Transistor channel width tapering in serially connected MOSFET chains decreases propagation delay and fall times, and reduces the power dissipation. Tapering is the process of changing the size of each transistor width within the serial chain, such that the largest transistor is connected to the power supply rail and the smallest transistor is connected to the output node. Analytical approaches are used to determine the optimal tapering factor for the serially connected MOSFET chain. Under a constant area constraint, the area gained from unscaled transistor widths is reallocated to the transistors using empirical approaches such that the overall delay is improved.
Keywords :
MOSFET; capacitance; delays; channel width tapering; constant area constraint; fall times; optimal tapering factor; overall delay; power dissipation; propagation delay; serially-connected MOS transistors; unscaled transistor widths; CMOS logic circuits; CMOS technology; Frequency estimation; Logic devices; MOSFET circuits; Parasitic capacitance; Power dissipation; Power supplies; Propagation delay; Rails;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187271
