A new register design for low power TLB and cache

This paper presents a new register design, called content-change-aware (CCA) register, to reduce the TLB/cache power consumption without delay penalty. By embedding the detection logic in the register, the CCA register is able to sense out the difference between the coming value and the current stored value. This property can be used to accurately filter out all the redundant TLB/cache accesses in real-time. We remove the comparison delay penalty from the conventional block buffering without impairing the power reduction efficiency. Applying the proposed CCA register to the TLB/cache with a single block buffer, the experimental results show that our design can drastically reduce the average power consumption per TLB/cache access as achieved by using the block buffering, but without compromise of system performance.