Automatic insertion of fault-tolerant structures at the RT level

Historically, there has been a lack of CAD tools for the design of on-line testable circuits. As a consequence, the design of on-line testable circuits is currently being made manually to a large extent. In this paper we propose a new tool for the automatic insertion of fault-tolerant structures in an HDL synthesizable description of the design. With this tool, a fault-tolerant version of the design can be automatically produced according to the user specifications. The resulting fault-tolerant design is also described in an HDL and can be simulated and synthesized with commercial tools. Examples are shown to demonstrate the capabilities of this approach