A full E-beam 0.25 mu m bipolar technology with sub-25 ps ECL gate delay

Author

Warnock, J. ; Cressler, J.D. ; Coane, P.J. ; Chiong, K.N. ; Rothwell, M.E. ; Jenkins, K. ; Burghartz, J.N. ; Petrillo, E. ; Mazzeo, N. ; Megdanis, A. ; Hohn, F.J. ; Thomson, M.G.R. ; Sun, J.Y.C. ; Tang, D.D.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1991

fDate

8-11 Dec. 1991

Firstpage

956

Lastpage

958

Abstract

The full leverage offered by E-beam lithography has been exploited in a 0.25- mu m bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25- mu m-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA.<>

Keywords

bipolar integrated circuits; delays; electron beam lithography; emitter-coupled logic; integrated circuit technology; integrated logic circuits; 0.25 micron; 1.1 mA; 24 ps; 33 GHz; E-beam lithography; ECL gate delay; bipolar technology; emitter coupled logic; overlay capability; submicron process; switching current; Capacitors; Circuit simulation; Cutoff frequency; Delay; Electrons; Lithography; Personnel; Predictive models; Switches; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0243-5

Type

conf

DOI

10.1109/IEDM.1991.235267

Filename

235267