Title :
Fast configurable polynomial division for error control coding applications
Author :
Monteiro, Fabrice ; Dandache, Abbas ; Lepley, Bernard
Author_Institution :
LICM, Metz Univ., France
Abstract :
The motivation for this paper is the need for high levels of reliability in modern telecommunication systems requiring very high data transmission rates. The search for technologically independent solutions, easy to implement on low cost and popular devices such as FPGA is an important issue. In this paper, we present a method to improve effectively the speed performance of the polynomial division performed in most error detecting and error correcting circuits. It is based on a pipeline structure for the polynomial division. Furthermore, the proposed solution is fully configurable, both from the static and the dynamic points of view. At synthesis stage, the parallelism level (size of the pipeline structure) and the maximal size of the polynomial divisor must both be chosen. Afterwards, the actual divisor can be chosen and changed while the circuit is running. The architecture proved to be very effective, as data rates up to 2.5 Gbits/s have been reached
Keywords :
dividing circuits; error correction codes; field programmable gate arrays; pipeline arithmetic; polynomials; 2.5 Gbit/s; FPGA; data transmission; error control coding; error correcting circuit; error detecting circuit; fast configurable polynomial division; parallel architecture; pipeline structure; reliability; telecommunication system; Circuits; Clocks; Costs; Data communication; Error correction; Field programmable gate arrays; Pipeline processing; Polynomials; Telecommunications; Throughput;
Conference_Titel :
On-Line Testing Workshop, 2001. Proceedings. Seventh International
Conference_Location :
Taormina
Print_ISBN :
0-7695-1290-9
DOI :
10.1109/OLT.2001.937836