Title :
Truncation Scheme for Recursive Multipliers
Author :
Bharkhada, Paresh ; Muscedere, Roberto ; Wu, Huapeng
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada
Abstract :
New truncation scheme is proposed for fixed width recursive multipliers. The architecture has been analyzed for errors and hardware savings. Error analysis shows the maximum error bound of approximately 0.6 for one-level fixed width recursive multipliers. An architectural analysis shows complexity saving of approximately 25% and even higher for higher level of recursion. The new scheme exhibits significant improvements in error and complexity with respect to previous recursive fixed-width architectures.
Keywords :
digital arithmetic; error analysis; architectural analysis; error analysis; fixed-width architectures; hardware savings; maximum error bound; one-level fixed width recursive multipliers; truncation scheme; Adders; Arrays; Complexity theory; Computers; Hardware; Logic gates; Proposals;
Conference_Titel :
Computer and Management (CAMAN), 2011 International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-9282-4
DOI :
10.1109/CAMAN.2011.5778785
