Title :
Low-power CMOS at Vdd = 4kT/q
Author :
Bryant, Andres ; Brown, Jeffrey ; Cottrell, Peter ; Ketchen, Mark ; Ellis-Monaghan, John ; Nowak, E.J.
Author_Institution :
IBM Micrielectron. Div., Essex Junction, VT, USA
Abstract :
Summary form only given. This paper reports a CMOS inverter active power-delay product of less than 0.1 fJ/stage at 25/spl deg/C and at Vdd=0.1 V. We believe this is the lowest reported. This is accomplished by using a novel technique to match NFET and PFET subthreshold currents and, thus, enable operation of a standard 1.5 V 180 nm CMOS technology in subthreshold at very low Vdd. This technique uses voltage feedback to the MOSFET wells to match the NFET off current (Ioffn) and PFET off current (Ioffp), significantly enhancing the manufacturability of CMOS subthreshold logic.
Keywords :
CMOS logic circuits; feedback; low-power electronics; threshold logic; 0.1 V; 1.5 V; 180 nm; 25 C; CMOS subthreshold logic; MOSFETs; inverter active power-delay product; low-power CMOS; n-FET offcurrent; n-channel FET subthreshold currents; p-FET offcurrent; p-channel FET subthreshold currents; standard CMOS technology; voltage feedback; CMOS technology; Circuits; Delay estimation; FETs; Inverters; MOSFETs; Microelectronics; Parasitic capacitance; Regulators; Voltage;
Conference_Titel :
Device Research Conference, 2001
Conference_Location :
Notre Dame, IN, USA
Print_ISBN :
0-7803-7014-7
DOI :
10.1109/DRC.2001.937856
