Quasi-planar NMOS FinFETs with sub-100 nm gate lengths

Double-gate MOSFETs alleviate short channel effects and allow for more aggressive device scaling. Simulations have shown that scaling double-gated devices can reach 10 nm. In the past, process complexity has prevented serious development of a scalable double-gate device. In 1998, Hisarnoto et al. introduced a FinFET process that provided a method of fabricating devices with promising performance and scalability. Using a single poly layer across a silicon fin to form both gates in the double-gate structure, the FinFET benefits from having equally-sized, self-aligned gates. In this work, we have revamped the FinFET process flow to make it simpler. This improved process flow still has the self-aligned, double-gate advantage without suffering from extra gate-to-drain overlap capacitance.