Title :
On random pattern testability of cryptographic VLSI cores
Author :
Schubert, A. ; Anheier, W.
Author_Institution :
Inst. fur Theor. Elektrotech. und Mikroelektron., Bremen Univ., Germany
Abstract :
In this paper, we show that the statistical qualities of cryptographic basic operations are the reason for the excellent pseudorandom testability of cryptographic processor cores. For the examination, typical basic operations of modern cryptographic algorithms are categorized in classes and analyzed regarding their pseudorandom properties. As an example, a global BIST for a cryptographic processor core based on the symmetric block encryption algorithm 3WAY is developed and analyzed. Finally, the quality of the proposed test architecture is determined by fault simulations.
Keywords :
VLSI; automatic test pattern generation; built-in self test; cryptography; data flow graphs; design for testability; embedded systems; fault simulation; integrated circuit testing; microprocessor chips; cryptographic VLSI cores; cryptographic algorithms; cryptographic basic operations; cryptographic processor cores; data flow graph; data path; fault simulations; global BIST; on-chip security modules; pseudorandom testability; random pattern testability; statistical qualities; subkey generation; symmetric block cipher algorithm; symmetric block encryption algorithm; test architecture quality; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Cryptography; Hardware; Logic testing; Security; Very large scale integration;
Conference_Titel :
European Test Workshop 1999. Proceedings
Conference_Location :
Constance, Germany
Print_ISBN :
0-7695-0390-X
DOI :
10.1109/ETW.1999.803820