DocumentCode :
3302441
Title :
Functional and structural testing of switched-current circuits
Author :
Renovell, M. ; Azaïs, F. ; Bodin, J.-C. ; Bertrand, Y.
Author_Institution :
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear :
1999
fDate :
25-28 May 1999
Firstpage :
22
Lastpage :
27
Abstract :
This paper aims at defining an efficient test strategy for switched-current circuit testing. Taking into account the specificity of these circuits, we propose an original structural test technique as an alternative to traditionally-used functional verification. This technique is validated both at the cell and block levels. Test results demonstrate that a high fault coverage can be achieved with a low cost test procedure. A mixed strategy combining benefits of functional and structural approaches is derived.
Keywords :
CMOS analogue integrated circuits; integrated circuit testing; switched current circuits; block level validation; cell level validation; divide-by-two example; efficient test strategy; functional testing; high fault coverage; low cost test procedure; memory cell principle; mixed A/D designs; mixed strategy; structural testing; switched-current circuits; Analog circuits; Analog integrated circuits; Analog-digital integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Costs; Silicon compounds; Switching circuits; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Test Workshop 1999. Proceedings
Conference_Location :
Constance, Germany
Print_ISBN :
0-7695-0390-X
Type :
conf
DOI :
10.1109/ETW.1999.803821
Filename :
803821
Link To Document :
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