Title :
50 nm vertical surround gate MOSFET with S-factor of 75mV/dec
Author :
Ruigang Li ; Yaohui Zhang ; Yang Lu ; Choi, D.S. ; Luo, M. ; Wang, K.L.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
Vertical MOSFETs (VMOS) have the potential to improve short channel effects and to increase the integration density. Vertical replacement-gate (VRG) MOSFETs with 50 nm channel length on 300 nm Si wall and vertical sub-100 nm MOSFETs on MBE Si island by electric field tailing have been reported. In this paper, we report the fabrication and device characteristics along with simulation results of fully depleted vertical MOSFETs.
Keywords :
MOSFET; semiconductor device models; 300 nm; 50 nm; Si; channel length; self-aligned process; simulation; threshold voltage; vertical surround gate MOSFET; Etching; Fabrication; MOSFET circuits; Random access memory; Reluctance generators; Rough surfaces; Silicides; Surface resistance; Surface roughness; Threshold voltage;
Conference_Titel :
Device Research Conference, 2001
Conference_Location :
Notre Dame, IN, USA
Print_ISBN :
0-7803-7014-7
DOI :
10.1109/DRC.2001.937873
