Enhanced performance of accumulation mode 0.5 mu m CMOS/SOI operated at 300 K and 85 K

Author

Wang, L.K. ; Seliskar, J. ; Bucelot, T. ; Edenfeld, A. ; Haddad, N.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1991

fDate

8-11 Dec. 1991

Firstpage

679

Lastpage

682

Abstract

A 0.5 mu m fully depleted CMOS on thin SOI (silicon-on-insulator) VLSI technology has been developed for SRAM and logic applications. Using a normally off, accumulation mode SOI device design with the source/drain/substrate having the same doping polarity, the device transconductance, mobility, and gate delay are improved by 40% over conventional enhancement mode devices. By cooling the devices to liquid nitrogen temperature, both n- and p-channel devices show improvement in mobility and transconductance, reduction of subthreshold slopes, and an increase of breakdown voltages from the floating substrates.<>

Keywords

CMOS integrated circuits; SRAM chips; VLSI; carrier mobility; integrated logic circuits; semiconductor-insulator boundaries; 0.5 micron; 300 K; 85 K; SRAM; accumulation mode; breakdown voltages; doping polarity; floating substrates; fully depleted CMOS; gate delay; logic applications; mobility; normally off devices; performance; subthreshold slopes; thin SOI; transconductance; CMOS logic circuits; CMOS technology; Cooling; Delay; Doping; Logic devices; Random access memory; Silicon on insulator technology; Transconductance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0243-5

Type

conf

DOI

10.1109/IEDM.1991.235331

Filename

235331