Title :
Selecting Partial Scan Flip-flops For Circuit Partitioning
Keywords :
Automatic test pattern generation; Circuit testing; Flip-flops; Hardware; National electric code; Partitioning algorithms; Scheduling algorithm; Sequential analysis; Sequential circuits; Test pattern generators;
Conference_Titel :
Computer-Aided Design, 1994., IEEE/ACM International Conference on
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1994.629890
