• DocumentCode
    3303274
  • Title

    Logic Synthesis Techniques For Reduced Area Implementation Of Multilevel Circuits With Concurrent Error Detection

  • Author

    Touba, Nur A. ; McCluskey, Edward J.

  • fYear
    1994
  • fDate
    6-10 Nov 1994
  • Firstpage
    651
  • Lastpage
    654
  • Keywords
    Circuit faults; Circuit synthesis; Circuit testing; Computer errors; Concurrent computing; Electrical fault detection; Fault detection; Logic circuits; Parity check codes; Process design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1994., IEEE/ACM International Conference on
  • ISSN
    1063-6757
  • Print_ISBN
    0-8186-3010-8
  • Type

    conf

  • DOI
    10.1109/ICCAD.1994.629891
  • Filename
    629891
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3303274