Title :
Logic Synthesis Techniques For Reduced Area Implementation Of Multilevel Circuits With Concurrent Error Detection
Author :
Touba, Nur A. ; McCluskey, Edward J.
Keywords :
Circuit faults; Circuit synthesis; Circuit testing; Computer errors; Concurrent computing; Electrical fault detection; Fault detection; Logic circuits; Parity check codes; Process design;
Conference_Titel :
Computer-Aided Design, 1994., IEEE/ACM International Conference on
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1994.629891
