Title :
Hot-carrier effects in surface-channel PMOSFETs with BF/sub 2/- or boron-implanted gates
Author :
Mogami, T. ; Johansson, L.E.G. ; Sakai, I. ; Fukuma, M.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
Hot-carrier effects for surface-channel PMOSFETs with p/sup +/ poly-Si gates were investigated. When the annealing temperature is higher and the gate oxide thickness is thinner, larger boron penetration is observed for p/sup +/ poly-Si PMOSFETs. As a dopant for poly-Si gates, BF/sub 2/ causes larger boron penetration. However, PMOSFET lifetime does not depend on the degree of boron penetration, but on doping species (BF/sub 2/ or boron). PMOSFETs with BF/sub 2/-implanted gates have about 100 times longer lifetime than those with boron-implanted gates, because electron trapping in the gate oxide with the BF/sub 2/-implanted gate is smaller due to the incorporation of fluorine. The maximum allowed supply voltage, based on the hot-carrier reliability, is higher than mod -4 mod V for sub half-micron PMOSFETs with p/sup +/ poly Si gates.<>
Keywords :
annealing; electron traps; hot carriers; insulated gate field effect transistors; ion implantation; reliability; B implanted gates; B penetration; BF/sub 2/-implanted gates; Si:B; Si:BF/sub 2/; annealing temperature; electron trapping; gate oxide thickness; hot-carrier reliability; p/sup +/ poly-Si gates; supply voltage scaling; surface-channel PMOSFETs; Annealing; Boron; Doping; Electrodes; Electron traps; Hot carrier effects; MOSFETs; Stress; Temperature; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235339
