Title :
Optimization Of Hierarchical Designs Using Partitioning And Resynthesis
Author :
Eikerling, Heinz-Josef ; Hunstock, Ralf ; Camposano, Raul
Keywords :
Automata; Automatic control; Boolean functions; Costs; Delay; Design optimization; Digital circuits; High level synthesis; Logic design; Logic gates;
Conference_Titel :
Computer-Aided Design, 1994., IEEE/ACM International Conference on
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1994.629900
