Title :
Provably Correct High-level Timing Analysis Without Path Sensitization
Author :
Bhattacharya, Subhrajit ; Dey, Sujit ; Brglez, Franc
Keywords :
Circuit analysis; Circuit synthesis; Clocks; Computer science; Delay estimation; Energy consumption; National electric code; Permission; Process design; Timing;
Conference_Titel :
Computer-Aided Design, 1994., IEEE/ACM International Conference on
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1994.629905
