High-performance 0.5 mu m CMOS technology for logic LSIs with embedded large capacity SRAMs

Author

Norishima, M. ; Yoshinari, H. ; Hayashida, H. ; Eguchi, T. ; Kasai, K. ; Shinagawa, H. ; Matsunaga, T. ; Matsuno, T. ; Shibata, H. ; Toyoshima, Y. ; Hashimoto, K.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1991

fDate

8-11 Dec. 1991

Firstpage

489

Lastpage

492

Abstract

The optimum device design of 0.5 mu m CMOS for logic LSIs with embedded large-capacity SRAMs (static RAMs) with a 3.3 V supply voltage is proposed. In order to attain high performance with a 3.3 V supply, the p-MOSFET structure was designed and the gate oxide thickness and junction capacitance were optimized. A poly-Si load SRAM cell with a triple-well structure on p-substrate, WSi-polycide gate electrode, and triple-level metallization with W plug via holes were implemented. By careful design of each parameter and proper integration of the technologies, a high-performance 0.5 mu m CMOS with large-capacity cache memories was realized.<>

Keywords

CMOS integrated circuits; SRAM chips; buffer storage; integrated circuit technology; integrated logic circuits; large scale integration; 0.5 micron; 3.3 V; CMOS technology; W plug via holes; WSi; WSi-polycide gate electrode; embedded large capacity SRAMs; gate oxide thickness; junction capacitance; large-capacity cache memories; logic LSIs; p-MOSFET structure; poly-Si load; polycrystalline Si; submicron IC technology; triple-level metallization; CMOS logic circuits; CMOS technology; Capacitance; Design optimization; Electrodes; Logic design; Logic devices; MOSFET circuits; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0243-5

Type

conf

DOI

10.1109/IEDM.1991.235349

Filename

235349