Title :
16 Mbit SRAM cell technologies for 2.0 V operation
Author :
Ohkubo, H. ; Horiba, S. ; Hayashi, F. ; Andoh, T. ; Kawaguchi, M. ; Ochi, Y. ; Soeda, M. ; Nozue, H. ; Miyamoto, H. ; Ohkawa, M. ; Shimizu, T. ; Sasaki, I.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
Novel memory cell technologies for 2.0-V cell operation of 16-Mb SRAMs (static RAMs) have been developed. These technologies have realized 7.2- mu m/sup 2/ cell size, 4.4 effective cell ratio for high noise immunity, and 10/sup 13/-A/cell leakage current. The key features of these technologies include: (1) a symmetrical cell configuration; (2) an access transistor with an N/sup -/ offset resistor; (3) a ground plate expanded on the cell area; and (4) a poly Si TFT (thin film transistor) with an LDO (lightly doped offset) structure, all of which are based on a 0.4- mu m design rule using a SAC (self aligned contact) process. The access transistor with an N/sup -/ offset resistor increases the cell ratio without expanding cell size. The symmetrical cell configuration, the ground plate, and the TFT with the LDO structure contribute to cell operation stability.<>
Keywords :
BiCMOS integrated circuits; CMOS integrated circuits; MOS integrated circuits; SRAM chips; integrated circuit technology; thin film transistors; 0.4 micron; 16 Mbit; 2 V; LDO structure; N/sup -/ offset resistor; SAC process; SRAM cell; access transistor; cell operation stability; ground plate; lightly doped offset; memory cell technologies; poly Si TFT; polycrystalline Si; self aligned contact; static RAMs; symmetrical cell configuration; thin film transistor; Driver circuits; Electrodes; Leakage current; MOSFETs; Random access memory; Resistors; Signal to noise ratio; Stability; Thin film transistors; Voltage;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235351
