A surrounding isolation-merged plate electrode (SIMPLE) cell with checkered layout for 256 Mbit DRAMs and beyond

The authors describe a novel cell structure called a surrounding isolation merged plate electrode (SIMPLE) cell. In this cell, close-packed silicon pillars are laid out checker-wise, and a thin isolation-merged plate electrode surrounds the pillars. This cell structure leads to cell area reduction to 50%, trench depth reduction to 50%, and planarization and process step reduction compared with the conventional trench type cell. Using the design rule of 64 Mbit DRAM (dynamic RAM) (0.35 mu m), the SIMPLE cell can achieve a cell area of 256 Mbit DRAM (0.5 mu m/sup 2/). The SIMPLE cell is an attractive candidate for 256 Mbit DRAMs and beyond.<>