DocumentCode
3303809
Title
Evolutionary strategies and intrinsic fault tolerance
Author
Tyrrell, A.M. ; Hollingworth, G. ; Smith, S.L.
Author_Institution
Dept. of Electron., York Univ., UK
fYear
2001
fDate
2001
Firstpage
98
Lastpage
106
Abstract
Redundancy is a critical component to the design of fault tolerant systems; both hardware and software. This paper explores the possibilities of using evolutionary techniques to first produce a processing system that will perform a required function, and then consider its applicability for producing useful redundancy that can be made use of in the presence of faults, ie is it fault tolerant? Results obtained using evolutionary strategies to automatically create redundancy as part of the “design” process are given. The experiments are undertaken on a Virtex FPGA with intrinsic evolution taking place. The results show that not only does the evolutionary process produce useful redundancy, it is also possible to reconfigure the system in real-time on the Virtex device
Keywords
evolutionary computation; fault tolerant computing; field programmable gate arrays; Virtex FPGA; evolutionary strategies; fault tolerant systems; intrinsic fault tolerance; redundancy; Centralized control; Computer architecture; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Hardware; Logic arrays; Real time systems; Redundancy; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Evolvable Hardware, 2001. Proceedings. The Third NASA/DoD Workshop on
Conference_Location
Long Beach, CA
Print_ISBN
0-7695-1180-5
Type
conf
DOI
10.1109/EH.2001.937951
Filename
937951
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