• DocumentCode
    3303905
  • Title

    An in-system routing strategy for evolvable hardware programmable platforms

  • Author

    Aróstegui, M. Moreno ; Sanchez, E. ; Cabestany, J.

  • Author_Institution
    Dept. of Electron. Eng., Tech. Univ. of Catalunya, Barcelona, Spain
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    157
  • Lastpage
    166
  • Abstract
    On of the major limiting factors for the development of hardware platforms able to support evolvable hardware principles is the lack of simple and compact in-system dynamic routing strategies. In this paper we shall present a programmable hardware architecture whose internal organization permits to perform dynamic routing processes. The architecture is based on a regular bi-dimensional array of functional cells. A hierarchical layered organization has been provided for these cells. Specific routing resources have been included in one of these layers, so that they permit to construct in an incremental way routing paths among the functional cells. The dynamic routing strategy is based on a replication process that is able to connect a source cell with various target cells. One of the major advantages of the proposed routing strategy lies in the fact that its complexity grows only linearly with the array size. Furthermore it is scalable, accommodating without performance degradation to any array size. Behavioral hardware descriptions haven been created for the functional cells that constitute the array. As the simulation and synthesis results will show, the proposed routing strategy will permit the implementation of actual evolvable hardware principles
  • Keywords
    computational complexity; digital simulation; field programmable gate arrays; behavioral hardware; complexity; dynamic routing; dynamic routing processes; dynamic routing strategy; evolvable hardware programmable platforms; functional cells; hardware platforms; hierarchical layered organization; in-system routing strategy; performance degradation; programmable hardware architecture; replication process; routing paths; simulation; Computer architecture; Computer science; Degradation; Field programmable gate arrays; Hardware; Laboratories; Logic; Routing; System-on-a-chip; Velocity measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Evolvable Hardware, 2001. Proceedings. The Third NASA/DoD Workshop on
  • Conference_Location
    Long Beach, CA
  • Print_ISBN
    0-7695-1180-5
  • Type

    conf

  • DOI
    10.1109/EH.2001.937957
  • Filename
    937957