Title :
Design of submicron PMOSFETs for DRAM array applications
Author :
El-Kareh, B. ; Abadeer, W.W. ; Tonti, W.R.
Author_Institution :
IBM, Essex Junction, VT, USA
Abstract :
A comparison is made between surface-channel P/sup +/ polysilicon gate and buried-channel N/sup +/ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the ´end-of-life´ magnitude of subthreshold off-current at zero gate-to-source voltage, projected from accelerated hot-carrier stress. Shifts in off-current depend on changes in threshold voltage and subthreshold slope. The minimum channel length which satisfies the lifetime criterion of 100% shift in off-current for surface channels is 0.3 mu m. The minimum channel length of buried channels must be increased by approximately=0.25 mu m over that of surface channels to meet the same lifetime criterion. This results in a reduction in drain current of approximately=30%.<>
Keywords :
CMOS integrated circuits; DRAM chips; insulated gate field effect transistors; integrated circuit technology; 0.3 micron; 3.3 V; 3.3 V CMOS technology; CMOS; DRAM arrays; MOSFET; N/sup +/ polysilicon gate; P/sup +/ polysilicon gate; accelerated hot-carrier stress; buried channels; lifetime criterion; minimum channel length; polysilicon gate PMOSFETs; submicron PMOSFETs; subthreshold off-current; subthreshold slope; surface channels; switching devices; threshold voltage; zero gate-to-source voltage; Acceleration; Boron; CMOS technology; Degradation; Hot carrier effects; Hot carriers; MOSFETs; Random access memory; Stress; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235374
