DocumentCode
3304014
Title
Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability
Author
Inuishi, M. ; Mitsui, K. ; Kusunoki, S. ; Oda, H. ; Tsukamoto, K. ; Akasaka, Y.
Author_Institution
Mitsubishi Electr. Corp., Hyogo, Japan
fYear
1991
fDate
8-11 Dec. 1991
Firstpage
371
Lastpage
374
Abstract
The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.<>
Keywords
capacitance; insulated gate field effect transistors; semiconductor device models; LCR meter; MOSFETs; four-terminal method; gate N/sup -/ overlap LDD transistor; gate capacitance characteristics; gate/drain capacitance; performance; reliability; Capacitance measurement; Capacitance-voltage characteristics; Electrodes; Electrons; Equations; Hot carriers; Impurities; Length measurement; Shadow mapping; Silicon compounds;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location
Washington, DC, USA
ISSN
0163-1918
Print_ISBN
0-7803-0243-5
Type
conf
DOI
10.1109/IEDM.1991.235376
Filename
235376
Link To Document