• DocumentCode
    3304283
  • Title

    Algorithm of defining 1-D indexing for M-D mixed radix FFT implementation

  • Author

    Ju, Chwen-Jye

  • Author_Institution
    Sharp Microelectronics Technology, Inc., Camas, WA, USA
  • Volume
    2
  • fYear
    1993
  • fDate
    19-21 May 1993
  • Firstpage
    484
  • Abstract
    A novel M-D (multidimensional) to 1-D FFT (fast Fourier transform) signal flow graph mapping is proposed. Thus, the M-D FFT can be efficiently implemented by the unified 1-D indexing, and the address generator design can be simplified. In addition, the matrix transposition is no longer necessary. The addressing sequences can be derived from the factorization of the twiddle factor matrix. The unified indexing concept of the M-D FFT implementation automatically solves the scaling problem of the block floating-point arithmetic. Practical chip design considerations in implementing the algorithm are presented
  • Keywords
    digital signal processing chips; fast Fourier transforms; floating point arithmetic; integrated circuit design; matrix decomposition; multidimensional systems; signal flow graphs; signal processing; address generator design; algorithm; block floating-point arithmetic; chip design; fast Fourier transform; mixed radix FFT; multidimensional FFT; scaling; signal flow graph mapping; twiddle factor matrix; unified 1-D indexing; Chip scale packaging; Digital signal processing chips; FETs; Fast Fourier transforms; Flow graphs; Indexing; Microelectronics; Multidimensional signal processing; Signal mapping; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on
  • Conference_Location
    Victoria, BC
  • Print_ISBN
    0-7803-0971-5
  • Type

    conf

  • DOI
    10.1109/PACRIM.1993.407316
  • Filename
    407316